The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device in which a memory cell consists of a MISFET (metal insulated semiconductor field effect transistor) which has a floating gate electrode and a control gate electrode, and in which the data is written by injecting carriers into the floating gate electrode.
One type of non-volatile memory is an EEPROM (electrically erasable and programmable ROM, and wherein the memory thereof can be constituted by cells therefor which include a single MISFET that has a floating gate electrode and a control gate electrode as has been disclosed in the IEDM Technical Digest, 1985, pp. 616-617. In this memory cell, the data is written by applying a voltage of 12.5 volts to the control gate electrode, a voltage of 8 volts to the drain and a voltage of zero volt to the source, such that a drain current of, for example, about 500 .mu.A flows to generate hot electrons at the drain end that will be injected to the floating gate electrode. The data, on the other hand, is erased by applying a voltage of 12.5 volts to the source and a voltage of zero volt to the drain and to the control gate electrode, so that the electrons in the floating gate electrode are emitted into the substrate.
It is, however, a recent trend to employ only one power source for the semiconductor memory device, i.e., to employ a power source of, for instance, 5 volts only instead of employing a plurality of power sources to supply power to a semiconductor chip. Therefore, high voltages such as of 12.5 volts and 8 volts are obtainable by booster circuits provided in the semiconductor chip. However, booster circuit which consists of a diode and a capacitor requires an increased area when it is designed to provide an increased current capacity. Usually, however, the booster circuit is designed to have a current capacity of about 100 .mu.A. Therefore, the drain current is not sufficient enough for effectively writing the data, and good writing characteristics are not obtainable.
To erase the data, furthermore, a voltage of as high as 12.5 volts must be applied to the source. However, the breakdown voltage is small between the source and the substrate, and a large leakage current flows into the substrate thereby making it difficult to apply a voltage of as high as 12.5 volts to the source.
There was earlier proposed by some of the applicants of the present application, a semiconductor memory device in connection with U.S. application Ser. No. 053,730, which is commonly assigned, in which a p.sup.+ -type layer was formed in contact with the drain so as to surround the drain to improve writing characteristics, and an n-type layer was formed on the outside of the n.sup.+ -type layer to increase the ]unction breakdown voltage between the source and the substrate. By forming the drain in the p.sup.+ -type layer, as described above, the electric field is intensified at an end on the channel side of the drain when the data is being written, and whereby hot electrons are generated highly efficiently contributing to improving the writing characteristics. With reference to the source, on the other hand, the avalanche breakdown voltage thereof is increased relative to the substrate, and the data is erased by applying a voltage which is as high as about 12.5 volts maintaining improved erasing characteristics.